Panel Layout Verification
Total support for FPD layout verification from pixel cell characteristic analysis to top panel DRC/ERC/LVS/LPE verification
- Full panel high-speed DRC/ERC/LVL verification by hierarchical processing
- High-speed, high-accuracy verification for the entire array
Interactive DRC/LVS Tool
SX-Meister iDRC / iLVS
■Reduce sign-off verification time
- Debug environment that allows easy layout modification
- Real-time DRC linked with layout input/editing
- High-precision DRC compatible with any-angle figures
- Acceleration of array verification by hierarchical processing
- LVS that supports special LCD device recognition
- Design rules can be easily created and edited using the GUI
- Rule import of third-party verification tool
LVL Tool for FPD
SX-Meister FineLVL
■Supports comparative verification of layout patterns
- Pattern comparison of a specific layer
- Pattern comparison between hierarchical cells
- Hierarchical consistency comparison
- Simple rule definition
- Supports flat processing of layers
ERC Tool for FPD
SX-Meister FineERC
■Supports wiring open and short check
- Equipotential tracking and verification of polygon figures
- High-speed verification of pixel array by hierarchical processing
- Short path search
- Simple rule definition